HME-M7 family FPGA is integrated with the ARM Cortex™-M3 32-bit RISC core, high performance FPGA, and plenty of peripherals. This high-performance core works at 300 MHz frequency, with a Memory Protection Unit (MPU) and high-speed embedded memories (Code RAM memory up to 128 Kbytes with 8K code cache and data RAM up to 64 Kbytes). Also, HME-M7 fulfills customized system design and IP using the programmable logic resources, embedded RAM blocks and DSPs.
The device offers dual 12-bit 1MSPS ADC, four general-purpose 32-bit timers which can be used as time bases. Moreover, it contains standard and advanced communication interfaces: I2Cs and SPIs, USARTs, ethernet, dual CAN and a USB, as well as include a real-time clock.
The 16bit DDR2/3 hard controller can meet the large and high-speed data memory with access requirements. The AHB bus is used to connect the FPGA, ARM core and the peripherals. A high-performance internal AHB system bus interconnects the embedded processor, its peripherals, and the FPGA at a maximum speed of 300MHz.
The bus simultaneously provides 32 bits of read data, 32 bits of write data, and a 32-bit address. Multiple bus masters arbitrate for bus access. Potential bus masters include the ARM Cortex™-M3 processor, the read and write channels of each DMA channel, the JTAG interface, and FPGA fabric.
Feature
High Performance SRAM-based FPGA
High-performance, low-power consumption, 32-bit RlSC processor (ARM@ Cortex™-M3)
Performance up to 200MHz
Dual 12 bit 1MSPS ADC and other standard Peripherals
Multi-voltage, multi-standard, multi-banks I/O and packages
Richness of peripherals devices with ETH, USB, CAN, DMA controlers and DDR
8 external input clocks, 1 external crystal clock input
Embedded DSPs block
Based on efuse and SPl Flash security settings
Part Numberr |
M7A12N0 |
M7A12N5 | M7M12N5 | ||
Programmable Logic Block(PLB) |
LUT |
11520 |
11520 | 11520 | |
Register |
7680 |
7680 | 7680 | ||
Embedded Memory Block (EMB) |
4.5Kb |
144 |
144 | 144 | |
Max |
648Kb |
648Kb | 648Kb | ||
SRAM | Code RAM | 128KB | 128KB | 128KB | |
Max | 128KB | 128KB | 128KB | ||
Data RAM | 64KB | 64KB | 64KB | ||
Max | 64KB | 64KB | 64KB | ||
SDRAM | - | - | 64Mb | ||
DSP | 48 | 48 | 48 | ||
PLL |
4 |
4 | 4 | ||
DLL | 4 | 4 | 4 | ||
Crystal | 1 | 1 | 1 | ||
Contex-M3 |
1 |
1 | 1 | ||
DDRII/III Controller |
1 |
1 | 1 | ||
USB High Speed OTG 2.0 & PHY | 1 | 1 | 1 | ||
ETH 10/100/1000M controller | 1 | 1 | 1 | ||
CAN 2.0 A/B | 2 | 2 | 2 | ||
12 bit 1MSPS ADC | 2 | 2 | 2 | ||
UART | 3 | 3 | 3 | ||
I2C | 2 | 2 | 2 | ||
SPI | 2 | 2 | 2 | ||
SPI Flash | 0 | 16Mb | 16Mb | ||
Max User I/O |
310 |
310 | 310 | ||
IPs |
Packages |
||||
LQFP144 | FBGA256 | FBGA484 | QFN88 | ||
RTC |
- |
1 |
1 | - | |
ADC |
8ch |
2ch |
14ch | 6ch | |
DDR data width |
- |
16bit |
16bit | - | |
User I/O (LVDS pairs) |
97(27) |
156(31) |
310(75) | 59(5) | |
Part Number |
|||||
M7A12N0 |
- |
Yes |
Yes | - | |
M7A12N5 |
Yes | - | - | Yes | |
M7M12N5 |
- |
- |
- | Yes |
Title | Version | Release Date | File Format |
HME-M7 Family_User Guide | V_1.7 | 2022-04-28 | |
HME-M7 Family_Data Sheet | V_2.2 | 2023-01-19 | |
HME-M7_pinlist | 2023-06-13 | Excel | |
HME-M7_Schematic Layout_User Guide | 2018-10-28 | ||
HME-M7 Family PS Programming_Application Notes | V_1.0 | 2019-08-06 |