HME-H1C02 is a low power and low cost programmable device integrated the extreme flexibility of an FPGA and enhanced 8051 MCU system for low power, low cost and small footprint target market. H1C02 supports video interfaces including MlPl@, MlPl DBl, CMOS camera and display interfaces, MlPl D-PHY, MIPI CSI-2, MIPI DS and SubLVDS. By using 40nm LP technology, HME-H1C02 FPGA is able to support 2K+ UHD in real-time high resolution, high-bandwidth mobile interface cameras and displays.
With the architecture, the device can be widely used in the markets of mobile, tablet, wearable, VR/AR, drone and smart home areas.
Great combination of MCU, MIPI and FPGA to realize high integration, flexible operation, and good expansibility;
High performance LUT6 architecture;
To implement the addition chain without logical resource;
Two hardened 4-Lane MIPI interfaces and controllers integrated;
Wafer Level Chip Scale (WLCSP) Package Specifications;
High-performance video MIPI bridge;
High cost-effective FPGA in the industry;
256bit AES key and 128bit initiation vector for bitstream decryption and other configuration setting data.
Part Number |
H1C02N3 |
|
Logic cells |
1,536 |
|
Programmable Logic Block (PLB) |
LUT4 |
1,536 |
Register |
1,024 |
|
Embedded Memory Block (EMB) |
4.5Kb |
16 |
Max |
72Kb |
|
PLL |
1 |
|
On-chip OSC |
1 |
|
MCU |
8051 | 1 |
UART | 2 | |
I2C | 1 | |
SPI | 2 | |
Timer | 3 | |
DMA | 1 | |
SRAM | 1K x 8b | 1 |
Total | 1KB | |
SPI Flash | 4Mb | |
eFuse |
256b |
|
Package (unit: mm) |
Max User I/O (LVDS Pairs) |
|
QFN32 (4x4x0.55, 0.4 pitch) |
24 (6) |
|
WLCSP33 (2.5x2.9x0.48, 0.4 pitch) |
23 (5) |
Title | Version | Release Date | File Format |
HME-H1C02 Family FPGA_Data Sheet | V_1.7 | 2023-05-12 | |
HME-H1C02_pinlist | Excel |