中(zhōng)文(wén)版
HME-H7 family device combines the extreme flexibility of FPGA with high performance Cortex-M3 MCU core, peripherals and large on chip SRAM.
HME-H7P20 is a high-performance device which can be used in a wide range of applications such as high performance MCU control and processing, as well as especially are optimized for embedded vision applications – supporting a variety of high bandwidth sensor and display interfaces, video processing such as LED display and TCON and industry control.
By using these configurable soft IP cores as standardized blocks, hardened IPs and MCU, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
Feature
SRAM-based FPGA Fabric
- 6-input Look-up Tables, up to 12K
- DFF-based registers, up to 23,040
- performance up to 220MHz
Embedded Memory Block
- 128 programmable dual-port DPRAM memory, 9Kbit
Embedded DSP Blocks (MAC)
- 32 multiplier blocks (18 x18)
or 64 multiplier blocks (18 x 9)
or 128 multiplier blocks (10 x 10)
Clock Network
- 32 de-skew global clocks
- 1 OSC, +/-5% frequency accuracy
- 2 PLLs
- dynamic clock management in system
I/O
- 3.3/2.5/1.8/1.5/1.2V LVTTL/LVCMOS general I/O
- programmable source synchronous I/O
- emulated MIPI D-PHY, LVDS Rx, LVDS Tx, BLVDS
- up to 1200Mb/s per LVDS I/O
MCU
ARM Cortex-M3 MCU
- high performance 32-bit processor, frequency up to 300MHz
- outstanding processing performance combined with fast interrupt handling
- enhanced system debug with extensive breakpoint and trace capabilities
- efficient processor core, system, and memories
- integrated sleep mode
Memory
Embeded SRAM Block
18 SRAM, 32Kx32bit Total 2.2MB
| Part Number | H7P20-M0H1 | H7P20-M1H1 | H7P20-M2H1 | H7P20-M0X1 | H7P20-M0A1 | |
|
Programmable Logic Block (PLB) |
Logic cells (K) | 20 | 20 | 20 | 20 | 20 |
| LUT6 | 11,520 | 11,520 | 11,520 | 11,520 | 11,520 | |
| Register | 23,040 | 23,040 | 23,040 | 23,040 | 23,040 | |
|
Embedded Memory Block (EMB) |
9Kb | 128 | 128 | 128 | 128 | 128 |
| Max (Kb) | 1,152 | 1,152 | 1,152 | 1,152 | 1,152 | |
| DSP | 18b*18b | 32 | 32 | 32 | 32 | 32 |
| PLL | 2 | 2 | 2 | 2 | 2 | |
| OSC | RC | 1 | 1 | 1 | 1 | 1 |
| MCU | Cortex-M3 | 1 | 1 | 1 | 1 | 1 |
| UART | 3 | 3 | 3 | 3 | 3 | |
| I2C | 3 | 3 | 3 | 3 | 3 | |
| SPI | 3 | 3 | 3 | 3 | 3 | |
| GPIO | 2 | 2 | 2 | 2 | 2 | |
| Timer | 2 | 2 | 2 | 2 | 2 | |
| WDG | 1 | 1 | 1 | 1 | 1 | |
| DMA | 1 | 1 | 1 | 1 | 1 | |
| SRAM | 128KB | 18 | 18 | 18 | 18 | 18 |
| Total (KB) | 2,256 | 2,256 | 2,256 | 2,256 | 2,256 | |
| pSRAM | 32Mb | 0 | 1 | 2 | 0 | 0 |
| Total (Mb) | 0 | 32 | 64 | 0 | 0 | |
| eFuse | 128b | 1 | 1 | 1 | 1 | 1 |
| Package (unit: mm) | Max user I/O (LVDS Pairs) | |||||
| LQFP176 (22.00x22.00, 0.4 pitch) | 151 (0) | 151 (0) | 151 (0) | - | - | |
| FBGA256 (17.00x17.00, 1.0 pitch) | - | - | - | 186 (0) | 179 (0) | |
| VFBGA324 (15.00x15.00, 0.8 pitch) | - | - | - | 210 (24) | - | |
| Title | Version | Release Date | File Format |
| HME-H7 Family FPGA_Data Sheet | V_2.1 | 2024-10-28 | |
| HME-H7_Family_FPGA_User_Guide | V_1.4 | 2023-11-27 | |
| HME-H7 Family FPGA Flyer_EN | V_2.0 | 2024-10-24 | |
| HME-H7 Family_Clock Resource_User Guide | V_1.0 | 2024-10-28 | |
| HME-H7_pinlist | V_1.6 | 2024-01-22 | Excel |
| H7 Family_PLL_User Guide_EN | V_1.0 | 2024-11-06 |
HME - H7P20(11)