HME - H1D03-Products Center

Great combination of MCU, MIPI and FPGA to realize high integration, flexible operation, and good expansibility;
High performance LUT6 architecture;
To implement the addition chain without logical resource;
Two hardened 4-lane MIPI interfaces and controller be integrated;
Wafer Level Chip Scale (WLCSP) package specifications;
High-performance video MIPI bridge;
High cost-effective FPGA in the industry.

Part Number		H1D03N0	H1D03N3	H1M03N3
Programmable Logic Block (PLB)	Logic cells	3,276	3,276	3,276
	LUT6	2,048	2,048	2,048
	Register	4, 096	4,096	4, 096
Embedded Memory Block (EMB)	4.5Kb	32	32	32
Embedded Memory Block (EMB)	Max (Kb)	144Kb	144Kb	144Kb
DSP	18b*18b	16	16	16
PLL		1	1	1
DLL		2	2	2
OSC		1	1	1
MIPI	D-PHY	2	2	2
MIPI	DSI Controller	2	2	2
MCU	8051	1	1	1
	UART	2	2	2
	I2C	1	1	1
	SPI	2	2	2
	Timer	3	3	3
	DMA	1	1	1
SRAM	2k x 32b	2	2	2
	8k x 32b	1	1	1
	Total	48KB	48KB	48KB
SPI Flash		0	4Mb	4Mb
Efuse		2x512b	2x512b	2x512b
pSRAM	4M*8b	-	-	2
Package (unit: mm)		Max User I/O (LVDS Pairs) / MIPI Lane
W72 (3.9x3.3x0.55, 0.4 pitch)		-	34 (10) / 8	-
W68 (4.0x4.6x0.55, 0.5 pitch)		-	-	21 (7) / 8
W58 (3.9x3.3x0.55, 0.4 pitch)			20 (3) / 8
L128 (16x16x1.2, 0.5 pitch)		58 (12) / 8	-	-

Application Cases

Title	Document ID	Version	Release Date	File Format
HME-H1D03 Family FPGA_Data Sheet		V_2.3	2024-11-12	PDF
HME-H1D03_pinlist		V_1.4	2023-05-16	Excel
HME-H1D03_schematic_reference_design(L128/W58/W68/W72)			2021-06-24	zip
HME_H1D03_Clock&PLL_Application Note		V_1.0	2020-04-18	PDF
HME_H1D03 In System Configuration_Application Note		V_1.0	2020-04-18	PDF
HME-H1D03_Family_FPGA_(Automotive)_DataSheet		V_1.0	2024-11-12	PDF