中(zhōng)文(wén)版
HME-P2 combines FPGA with high performance Cortex-M3 MCU core, peripherals, and on-chip SRAM.
lt is a high-performance device which can be widely used in many applications, such as high-performance in real time motion control and image processing. And especially, it is optimized for embedded vision applications and industry control which support high bandwidth MlPl and LVDS interfaces.
HME-P2 Family FPGA Features
SRAM-based FPGA Fabric
- 6-input Lookup Tables, up to 32K equivalent to 52K logic cells
- DFF-based registers, up to 65,280
Embedded Memory Block
- 196 programmable dual-port DPRAM memory, 9Kb, totaling 1,764Kb
Embedded DSPs block
- 96 DSP (MAC) blocks, 18x18
- or 384 10x10 DSP (MAC) blocks
Clock Network
- 32个de-skew global clocks
- 1 OSC, ±5% freguency accuracy
- 2 PLLs
- dynamic clock management in system
I/O
- 3.3/2.5/1.8/1.5/1.2V LVTTL/LVCMOS常规I/O
- programmable source synchronous I/O
- emulated MIPI D-PHY, LVDS Rx, LVDS Tx, BLVDS
- up to 1200 Mb/s per LVDS I/O
Memory
Embedded SRAM Block
- 2 SRAM, 4Kx32b，totaling 32KB
Package
- SFBGA256
- VBGA324
MCU
ARM Cortex-M3 MCU
- high performance 32-bit processor, frequency up to 300MHz
- outstanding processing performance combined with fast interrupt handling
- enhanced system debug with extensive breakpoint and trace capabilities
- efficient processor core, system, and memories
- single cycle multiplication, hardware divide
- integrated sleep mode
Peripheral
- 2 Timer
- 1 Watch Dog Timer
- 3 I2C interfaces
- 3 SPI interfaces
- 1 QSPI interface
- 3 UART interface
- 2 GPIOs 32-bit
- 1 DMA
| Part Number | P2P50-M0X1 | P2P50-M4H1 | P2P50-M0H1 | |
|
Programmable Logic Block (PLB) |
Logic cells (K) | 52K | 52K | 52K |
| LUT6 | 32,640 | 32,640 | 32,640 | |
| Register | 65,280 | 65,280 | 65,280 | |
|
Embedded Memory Block (EMB) |
9Kb | 196 | 196 | 196 |
| Max (Kb)(1) | 1,764 | 1,764 | 1,764 | |
| DSP | 18b*18b(2) | 96 | 96 | 96 |
| PLL | 2 | 2 | 2 | |
| OSC | RC | 1 | 1 | 1 |
| MCU | Cortex-M3 | 1 | 1 | 1 |
| UART | 3 | 3 | 3 | |
| I2C | 3 | 3 | 3 | |
| SPI | 3 | 3 | 3 | |
| GPIO | 2 | 2 | 2 | |
| Timer | 2 | 2 | 2 | |
| WDG | 1 | 1 | 1 | |
| DMA | 1 | 1 | 1 | |
| SRAM | 4K*32b | 2 | 2 | 2 |
| Total (KB) | 32 | 32 | 32 | |
| pSRAM | 256Mb | 0 | 4 | 0 |
| Total (Mb) | 0 | 1024 | 0 | |
| eFuse | 128b | 1 | 1 | 1 |
| Package (unit: mm) | Max user I/O / (LVDS pair) | |||
| SFBGA256 (11.00x11.00, 0.65 pitch) | - | - | 189(72)(3) | |
| VFBGA324 (15.00x15.00, 0.8 pitch) | 213(24) | 207(24) | ||
Notes:
(1) No hard FlFO.
(2) Two 18x18 can achieve 35x35, and one 18x18 can achieve four10x10.
(3) 72 pairs are analogue output LVDS.
| Title | Version | Release Date | File Format |
| HME-P2_pinlist | V_3.1 | 2024-11-22 | Excel |
| HME-P2_Family_FPGA_Data_Sheet_EN | V_1.1 | 2023-10-07 | |
| HME-P2 Family_Clock Resource_User Guide_EN | V_1.0 | 2024-10-28 | |
| HME-P2 Family_PLL_User Guide_EN | V_1.0 | 2024-10-28 | |
| HME-P2_Family_FPGA_Flyer_EN | V_2.0 | 2024-10-24 |
HME - P2P50(7)